// Block Name (Original): TestLAD
// Block Number: 2
// Original Language: LAD

FUNCTION_BLOCK "TestLAD"
{ S7_Optimized_Access := 'TRUE' }
VERSION : 0.1

VAR_INPUT
END_VAR

VAR_OUTPUT
END_VAR

VAR_IN_OUT
END_VAR

VAR_TEMP
END_VAR

BEGIN

  // Network 1: Clock Bit

  // RLO: "Clock_10Hz"
  // Logic moved to Coil 26
  "Clock_5Hz" := "Clock_10Hz" AND NOT "M19001";\n"M19001" := "Clock_10Hz"; // P_TRIG("Clock_10Hz") (Mem update handled by consumer)

  // Network 2: Clock Bit

  // RLO: "Clock_10Hz"
  // Logic moved to Coil 26
  "Clock_5Hz" := NOT "Clock_10Hz" AND "M19001";\n"M19001" := "Clock_10Hz"; // N_TRIG("Clock_10Hz") (Mem update handled by consumer)

END_FUNCTION_BLOCK