Obsidean_VM/Clock_Signal.md at 6b51c9d523a6059328f68b9ed8427ca932229e47

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// Block Type: FC
// Block Name (Original): Clock Signal
// Block Number: 1860
// Original Network Languages: LAD

FUNCTION "Clock_Signal" : Void
{ S7_Optimized_Access := 'TRUE' }
VERSION : 0.1

VAR_TEMP
  Actual_Time : DInt;
  Timer_For_Clock : Word;
END_VAR

  #_2M : Bool; // Auto-generated temporary
BEGIN

  // Network 1: MIX - CLK_0.1S (Original Language: LAD)

  // Edge Logic handled by Coil 26
  "CLK_0.05S_SUPPORT" := "Clock_10Hz"; // P_TRIG("Clock_10Hz") - Mem: "CLK_0.05S_SUPPORT"

  "CLK_0.1S" := "Clock_10Hz" AND NOT "CLK_0.05S_SUPP OR T";
  "CLK_0.05S_SUPPORT" := "Clock_10Hz"; // P_TRIG("Clock_10Hz") - Mem: "CLK_0.05S_SUPPORT"

  // Network 2: MIX - CLK_0.2S (Original Language: LAD)

  // Edge Logic handled by Coil 26
  "CLK_0.1S_SUPPORT" := "Clock_5Hz"; // P_TRIG("Clock_5Hz") - Mem: "CLK_0.1S_SUPPORT"

  "CLK_0.2S" := "Clock_5Hz" AND NOT "CLK_0.1S_SUPP OR T";
  "CLK_0.1S_SUPPORT" := "Clock_5Hz"; // P_TRIG("Clock_5Hz") - Mem: "CLK_0.1S_SUPPORT"

  // Network 3: MIX - CLK_0.5S (Original Language: LAD)

  // Edge Logic handled by Coil 26
  "CLK_0.25S_SUPPORT" := "Clock_2Hz"; // P_TRIG("Clock_2Hz") - Mem: "CLK_0.25S_SUPPORT"

  "CLK_0.5S" := "Clock_2Hz" AND NOT "CLK_0.25S_SUPP OR T";
  "CLK_0.25S_SUPPORT" := "Clock_2Hz"; // P_TRIG("Clock_2Hz") - Mem: "CLK_0.25S_SUPPORT"

  // Network 4: MIX - CLK_0.8S (Original Language: LAD)

  // Edge Logic handled by Coil 26
  "CLK_0.4S_SUPPORT" := "Clock_1.25Hz"; // P_TRIG("Clock_1.25Hz") - Mem: "CLK_0.4S_SUPPORT"

  "CLK_0.8S" := "Clock_1.25Hz" AND NOT "CLK_0.4S_SUPP OR T";
  "CLK_0.4S_SUPPORT" := "Clock_1.25Hz"; // P_TRIG("Clock_1.25Hz") - Mem: "CLK_0.4S_SUPPORT"

  // Network 5: MIX - CLK_1.0S (Original Language: LAD)

  // Edge Logic handled by Coil 26
  "CLK_0.5S_SUPPORT" := "Clock_1Hz"; // P_TRIG("Clock_1Hz") - Mem: "CLK_0.5S_SUPPORT"

  "CLK_1.0S" := "Clock_1Hz" AND NOT "CLK_0.5S_SUPP OR T";
  "CLK_0.5S_SUPPORT" := "Clock_1Hz"; // P_TRIG("Clock_1Hz") - Mem: "CLK_0.5S_SUPPORT"

  // Network 6: MIX - CLK_2.0S (Original Language: LAD)

  // Edge Logic handled by Coil 26
  "CLK_0.8S_SUPPORT" := "Clock_0.625Hz"; // P_TRIG("Clock_0.625Hz") - Mem: "CLK_0.8S_SUPPORT"

  "CLK_1.6S" := "Clock_0.625Hz" AND NOT "CLK_0.8S_SUPP OR T";
  "CLK_0.8S_SUPPORT" := "Clock_0.625Hz"; // P_TRIG("Clock_0.625Hz") - Mem: "CLK_0.8S_SUPPORT"

  // Network 7: MIX - CLK_2.0S (Original Language: LAD)

  // Edge Logic handled by Coil 26
  "CLK_1.0S_SUPPORT" := "Clock_0.5Hz"; // P_TRIG("Clock_0.5Hz") - Mem: "CLK_1.0S_SUPPORT"

  "CLK_2.0S" := "Clock_0.5Hz" AND NOT "CLK_1.0S_SUPP OR T";
  "CLK_1.0S_SUPPORT" := "Clock_0.5Hz"; // P_TRIG("Clock_0.5Hz") - Mem: "CLK_1.0S_SUPPORT"

  // Network 8:  (Original Language: LAD)

  // Network 8 did not produce printable SCL code.

  // Network 9: Clock Generation (Original Language: LAD)
  //   Timer Loading

  "T105"(IN := "T105", PT := S5T#2M); // TODO: Declarar "T105" : TON;

  // Network 10:  (Original Language: LAD)
  //   MOVE For Change DATA-TYPE

  "Actual_Time" := "Timer_For_Clock";

  // Network 11: Clock 120 seconds (Original Language: LAD)

  "gClock_120s" := "Actual_Time" <= DINT;

  // Network 12: Clock 60 seconds (Original Language: LAD)

  "gClock_60s" := "Actual_Time" >= DINT;

  // Network 13: Clock 40 Seconds (Original Language: LAD)

  "gClock_40s" := "Actual_Time" >= DINT;

  // Network 14: Clock 20 Seconds (Original Language: LAD)

  "gClock_20s" := "Actual_Time" >= DINT;

END_FUNCTION
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