108 lines
3.4 KiB
Markdown
108 lines
3.4 KiB
Markdown
```pascal
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// Block Type: FC
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// Block Name (Original): Clock Signal
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// Block Number: 1860
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// Original Network Languages: LAD
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FUNCTION "Clock_Signal" : Void
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{ S7_Optimized_Access := 'TRUE' }
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VERSION : 0.1
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VAR_TEMP
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Actual_Time : DInt;
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Timer_For_Clock : Word;
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END_VAR
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#_2M : Bool; // Auto-generated temporary
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BEGIN
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// Network 1: MIX - CLK_0.1S (Original Language: LAD)
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// Edge Logic handled by Coil 26
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"CLK_0.05S_SUPPORT" := "Clock_10Hz"; // P_TRIG("Clock_10Hz") - Mem: "CLK_0.05S_SUPPORT"
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"CLK_0.1S" := "Clock_10Hz" AND NOT "CLK_0.05S_SUPP OR T";
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"CLK_0.05S_SUPPORT" := "Clock_10Hz"; // P_TRIG("Clock_10Hz") - Mem: "CLK_0.05S_SUPPORT"
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// Network 2: MIX - CLK_0.2S (Original Language: LAD)
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// Edge Logic handled by Coil 26
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"CLK_0.1S_SUPPORT" := "Clock_5Hz"; // P_TRIG("Clock_5Hz") - Mem: "CLK_0.1S_SUPPORT"
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"CLK_0.2S" := "Clock_5Hz" AND NOT "CLK_0.1S_SUPP OR T";
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"CLK_0.1S_SUPPORT" := "Clock_5Hz"; // P_TRIG("Clock_5Hz") - Mem: "CLK_0.1S_SUPPORT"
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// Network 3: MIX - CLK_0.5S (Original Language: LAD)
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// Edge Logic handled by Coil 26
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"CLK_0.25S_SUPPORT" := "Clock_2Hz"; // P_TRIG("Clock_2Hz") - Mem: "CLK_0.25S_SUPPORT"
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"CLK_0.5S" := "Clock_2Hz" AND NOT "CLK_0.25S_SUPP OR T";
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"CLK_0.25S_SUPPORT" := "Clock_2Hz"; // P_TRIG("Clock_2Hz") - Mem: "CLK_0.25S_SUPPORT"
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// Network 4: MIX - CLK_0.8S (Original Language: LAD)
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// Edge Logic handled by Coil 26
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"CLK_0.4S_SUPPORT" := "Clock_1.25Hz"; // P_TRIG("Clock_1.25Hz") - Mem: "CLK_0.4S_SUPPORT"
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"CLK_0.8S" := "Clock_1.25Hz" AND NOT "CLK_0.4S_SUPP OR T";
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"CLK_0.4S_SUPPORT" := "Clock_1.25Hz"; // P_TRIG("Clock_1.25Hz") - Mem: "CLK_0.4S_SUPPORT"
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// Network 5: MIX - CLK_1.0S (Original Language: LAD)
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// Edge Logic handled by Coil 26
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"CLK_0.5S_SUPPORT" := "Clock_1Hz"; // P_TRIG("Clock_1Hz") - Mem: "CLK_0.5S_SUPPORT"
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"CLK_1.0S" := "Clock_1Hz" AND NOT "CLK_0.5S_SUPP OR T";
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"CLK_0.5S_SUPPORT" := "Clock_1Hz"; // P_TRIG("Clock_1Hz") - Mem: "CLK_0.5S_SUPPORT"
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// Network 6: MIX - CLK_2.0S (Original Language: LAD)
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// Edge Logic handled by Coil 26
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"CLK_0.8S_SUPPORT" := "Clock_0.625Hz"; // P_TRIG("Clock_0.625Hz") - Mem: "CLK_0.8S_SUPPORT"
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"CLK_1.6S" := "Clock_0.625Hz" AND NOT "CLK_0.8S_SUPP OR T";
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"CLK_0.8S_SUPPORT" := "Clock_0.625Hz"; // P_TRIG("Clock_0.625Hz") - Mem: "CLK_0.8S_SUPPORT"
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// Network 7: MIX - CLK_2.0S (Original Language: LAD)
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// Edge Logic handled by Coil 26
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"CLK_1.0S_SUPPORT" := "Clock_0.5Hz"; // P_TRIG("Clock_0.5Hz") - Mem: "CLK_1.0S_SUPPORT"
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"CLK_2.0S" := "Clock_0.5Hz" AND NOT "CLK_1.0S_SUPP OR T";
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"CLK_1.0S_SUPPORT" := "Clock_0.5Hz"; // P_TRIG("Clock_0.5Hz") - Mem: "CLK_1.0S_SUPPORT"
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// Network 8: (Original Language: LAD)
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// Network 8 did not produce printable SCL code.
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// Network 9: Clock Generation (Original Language: LAD)
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// Timer Loading
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"T105"(IN := "T105", PT := S5T#2M); // TODO: Declarar "T105" : TON;
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// Network 10: (Original Language: LAD)
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// MOVE For Change DATA-TYPE
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"Actual_Time" := "Timer_For_Clock";
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// Network 11: Clock 120 seconds (Original Language: LAD)
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"gClock_120s" := "Actual_Time" <= DINT;
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// Network 12: Clock 60 seconds (Original Language: LAD)
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"gClock_60s" := "Actual_Time" >= DINT;
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// Network 13: Clock 40 Seconds (Original Language: LAD)
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"gClock_40s" := "Actual_Time" >= DINT;
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// Network 14: Clock 20 Seconds (Original Language: LAD)
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"gClock_20s" := "Actual_Time" >= DINT;
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END_FUNCTION
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```
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